275 lines
6.1 KiB
C++
275 lines
6.1 KiB
C++
//========= Copyright Valve Corporation, All rights reserved. ============//
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//
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// Purpose: win32 dependant ASM code for CPU capability detection
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//
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// $Workfile: $
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// $NoKeywords: $
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//=============================================================================//
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#if defined( _X360 ) || defined( WIN64 )
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bool CheckMMXTechnology(void) { return false; }
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bool CheckSSETechnology(void) { return false; }
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bool CheckSSE2Technology(void) { return false; }
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bool Check3DNowTechnology(void) { return false; }
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#elif defined( _WIN32 ) && !defined( _X360 )
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#pragma optimize( "", off )
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#pragma warning( disable: 4800 ) //'int' : forcing value to bool 'true' or 'false' (performance warning)
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// stuff from windows.h
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#ifndef EXCEPTION_EXECUTE_HANDLER
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#define EXCEPTION_EXECUTE_HANDLER 1
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#endif
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bool CheckMMXTechnology(void)
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{
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int retval = true;
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unsigned int RegEDX = 0;
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#ifdef CPUID
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_asm pushad;
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#endif
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__try
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{
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_asm
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{
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#ifdef CPUID
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xor edx, edx // Clue the compiler that EDX is about to be used.
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#endif
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mov eax, 1 // set up CPUID to return processor version and features
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// 0 = vendor string, 1 = version info, 2 = cache info
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CPUID // code bytes = 0fh, 0a2h
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mov RegEDX, edx // features returned in edx
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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// If CPUID not supported, then certainly no MMX extensions.
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if (retval)
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{
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if (RegEDX & 0x800000) // bit 23 is set for MMX technology
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{
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__try
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{
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// try executing the MMX instruction "emms"
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_asm EMMS
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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}
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else
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retval = false; // processor supports CPUID but does not support MMX technology
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// if retval == 0 here, it means the processor has MMX technology but
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// floating-point emulation is on; so MMX technology is unavailable
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}
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#ifdef CPUID
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_asm popad;
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#endif
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return retval;
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}
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bool CheckSSETechnology(void)
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{
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int retval = true;
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unsigned int RegEDX = 0;
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#ifdef CPUID
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_asm pushad;
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#endif
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// Do we have support for the CPUID function?
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__try
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{
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_asm
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{
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#ifdef CPUID
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xor edx, edx // Clue the compiler that EDX is about to be used.
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#endif
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mov eax, 1 // set up CPUID to return processor version and features
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// 0 = vendor string, 1 = version info, 2 = cache info
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CPUID // code bytes = 0fh, 0a2h
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mov RegEDX, edx // features returned in edx
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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// If CPUID not supported, then certainly no SSE extensions.
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if (retval)
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{
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// Do we have support for SSE in this processor?
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if ( RegEDX & 0x2000000L ) // bit 25 is set for SSE technology
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{
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// Make sure that SSE is supported by executing an inline SSE instruction
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// BUGBUG, FIXME - Visual C Version 6.0 does not support SSE inline code YET (No macros from Intel either)
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// Fix this if VC7 supports inline SSE instructinons like "xorps" as shown below.
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#if 1
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__try
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{
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_asm
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{
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// Attempt execution of a SSE instruction to make sure OS supports SSE FPU context switches
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xorps xmm0, xmm0
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// This will work on Win2k+ (Including masking SSE FPU exception to "normalized" values)
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// This will work on Win98+ (But no "masking" of FPU exceptions provided)
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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#endif
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{
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retval = false;
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}
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}
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else
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retval = false;
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}
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#ifdef CPUID
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_asm popad;
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#endif
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return retval;
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}
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bool CheckSSE2Technology(void)
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{
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int retval = true;
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unsigned int RegEDX = 0;
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#ifdef CPUID
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_asm pushad;
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#endif
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// Do we have support for the CPUID function?
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__try
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{
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_asm
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{
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#ifdef CPUID
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xor edx, edx // Clue the compiler that EDX is about to be used.
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#endif
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mov eax, 1 // set up CPUID to return processor version and features
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// 0 = vendor string, 1 = version info, 2 = cache info
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CPUID // code bytes = 0fh, 0a2h
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mov RegEDX, edx // features returned in edx
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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// If CPUID not supported, then certainly no SSE extensions.
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if (retval)
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{
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// Do we have support for SSE in this processor?
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if ( RegEDX & 0x04000000 ) // bit 26 is set for SSE2 technology
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{
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// Make sure that SSE is supported by executing an inline SSE instruction
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__try
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{
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_asm
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{
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// Attempt execution of a SSE2 instruction to make sure OS supports SSE FPU context switches
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xorpd xmm0, xmm0
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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}
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else
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retval = false;
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}
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#ifdef CPUID
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_asm popad;
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#endif
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return retval;
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}
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bool Check3DNowTechnology(void)
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{
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int retval = true;
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unsigned int RegEAX = 0;
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#ifdef CPUID
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_asm pushad;
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#endif
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// First see if we can execute CPUID at all
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__try
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{
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_asm
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{
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#ifdef CPUID
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// xor edx, edx // Clue the compiler that EDX is about to be used.
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#endif
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mov eax, 0x80000000 // setup CPUID to return whether AMD >0x80000000 function are supported.
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// 0x80000000 = Highest 0x80000000+ function, 0x80000001 = 3DNow support
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CPUID // code bytes = 0fh, 0a2h
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mov RegEAX, eax // result returned in eax
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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// If CPUID not supported, then there is definitely no 3DNow support
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if (retval)
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{
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// Are there any "higher" AMD CPUID functions?
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if (RegEAX > 0x80000000L )
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{
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__try
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{
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_asm
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{
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mov eax, 0x80000001 // setup to test for CPU features
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CPUID // code bytes = 0fh, 0a2h
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shr edx, 31 // If bit 31 is set, we have 3DNow support!
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mov retval, edx // Save the return value for end of function
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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retval = false;
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}
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}
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else
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{
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// processor supports CPUID but does not support AMD CPUID functions
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retval = false;
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}
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}
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#ifdef CPUID
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_asm popad;
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#endif
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return retval;
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}
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#pragma optimize( "", on )
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#endif // _WIN32
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